1. Field of the Invention
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a method for fabricating improved STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides of a field effect transistor.
2. Description of the Related Art
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC includes STI (Shallow Trench Isolation) structures that are formed within a semiconductor substrate 102. STI (Shallow Trench Isolation) structures include a first STI (Shallow Trench Isolation) trench 104 and a second STI (Shallow Trench Isolation) trench 106 formed within the semiconductor substrate 102. The first STI (Shallow Trench Isolation) trench 104 is filled with a first liner oxide 108 and a first STI (Shallow Trench Isolation) filler 110. Similarly, the second STI (Shallow Trench Isolation) trench 106 is filled with a second liner oxide 112 and a second STI (Shallow Trench Isolation) filler 114. The first STI filler 110 and the second STI filler 114 may be comprised of silicon dioxide for example.
Referring to FIG. 2, a MOSFET 200 is fabricated within an active device area between the two STI (Shallow Trench Isolation) trenches 104 and 106. The MOSFET 200 includes a drain extension 202 and a drain contact region 204 and includes a source extension 206 and a source contact region 208. The MOSFET 200 further includes a gate dielectric 210 and a gate structure 212 disposed over the gate dielectric 210. A spacer structure 214 is disposed on the sidewalls of the gate structure 212.
During fabrication of the MOSFET 200, acidic solutions, such as a solution of HF (hydrogen fluoride) is used for etching the various structures of the MOSFET 200. When the first STI filler 110 and the second STI filler 114 are comprised of silicon dioxide, such acidic solutions may etch away the first STI filler 110 and the second STI filler 114 resulting in a first divot 216 at the side of the first STI filler 110 facing the MOSFET 200 and in a second divot 218 at the side of the second STI filler 114 facing the MOSFET 200.
Silicide is formed for making contact with the drain, the source, and the gate of the MOSFET 200. A drain silicide 302 is formed in the drain contact region 204, a source silicide 304 is formed in the source contact region 208, and a gate silicide 306 is formed in the gate structure 212. Because the first divot 216 exposes the drain contact region 204 down toward the junction of the drain contact region 204, the drain silicide 302 extends down toward the junction of the drain contact region 204 near the first divot 216. Similarly, because the second divot 218 exposes the source contact region 208 down toward the junction of the source contact region 208, the source silicide 304 extends down toward the junction of the source contact region 208 near the second divot 218. The proximity of the drain silicide 302 to the junction of the drain contact region 204 results in undesired drain leakage current, and the proximity of the source silicide 304 to the junction of the source contact region 208 results in undesired source leakage current.
Thus, STI (Shallow Trench Isolation) structures that do not contribute to generation of such undesired leakage current through the drain and source of the MOSFET is desired.
Accordingly, in a general aspect of the present invention, STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures.
In one embodiment of the present invention, for forming shallow trench isolation structures, each of a pair of isolation trenches is etched through a layer of first dielectric material and a semiconductor substrate. The layer of first dielectric material is deposited on the semiconductor substrate. The pair of isolation trenches is filled with a second dielectric material with the second dielectric material extending up to fill the isolation trenches through the first dielectric material. The layer of first dielectric material is etched away such that sidewalls of the second dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A third dielectric material is conformally deposited on exposed surfaces of the second dielectric material filling the isolation trenches and on the semiconductor substrate. The third dielectric material is anisotropically etched such that the third dielectric material remains at the sidewalls of the second dielectric material exposed beyond the top of the semiconductor substrate. The third dielectric material has a different etch rate in an acidic solution from the second dielectric material filling the isolation trenches.
The present invention may be used to particular advantage when the layer of first dielectric material is comprised of silicon nitride on the semiconductor substrate comprised of silicon, and when the second dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the third dielectric material deposited on the sidewalls of the second dielectric material is comprised of silicon nitride.
In this manner, with the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.